In Multi-Chip-Module (MCM) packaging, test strategy is especially critical. Testing the final product, the conventional approach generally favored from the standpoint of both cost and reliability, is not optimum for MCM products since the final yield is a multiple of the yield for each individual die in the MCM package. For example, if each of the dies in the package has a yield of 95%, an MCM with 3 dies will have a yield of only 85.7%. Thus in some IC device packaging, notably MCM packaging, it becomes important to fully test the dies before assembly to identify the Known Good Dies (KGD).
Electrical testing of IC devices is a significant component of the cost of the final IC product. Thus, significant effort and expense is devoted to testing techniques and testing equipment. Testing of semiconductor IC devices is typically conducted using probe cards. This type of test equipment is highly developed and widely used. However, as the pitch of IC devices shrinks, it becomes difficult to reliably access the contact pads on the device. Parasitics of the contact such as the inductance of the probes can distort the measurement particularly with high speed RF ICs. Improvements in test equipment for IC chips have been made. A recent example is the so-called membrane tester described in U.S. Pat. No. 6,307,387, issued Oct. 31, 2001, parts of which are incorporated herein for an understanding of this invention, and all of which is incorporated by reference for additional details of this apparatus.
Membrane test instruments that are currently available for testing IC devices perform well for most digital IC devices, but are less effective for testing high speed analog IC devices, such as state of the art RF devices. Detecting errors in digital devices typically requires only sensing two voltage levels, VDD and VSS. Analog device testing is more demanding, and requires more efficient and sensitive test circuits. For the purpose of describing the invention as applied to IC devices in general, high-speed IC devices are those that process signals above 100 MHz.
A variety of test strategies are used in the IC industry. Preliminary tests at the wafer level may be performed to identify chips that pass DC and parametric tests, but testing the total functionality is often reserved until the IC device is singulated, and sometimes until the device is packaged. The DC and parametric tests cannot fully characterize the IC. It would be obviously desirable to perform full functional tests of RF chips at the wafer level, but that has been only marginally satisfactory using prior art test apparatus. Performing fully functional tests requires a test circuit that replicates the functions of the IC chip being tested. Input stimulants are applied to the chip under test and the electrical responses are compared with the reference test circuit to determine correlation. In typical prior art test apparatus, the reference circuits are necessarily located physically at a point removed from the device under test. Consequently, the electrical signals must travel significant lengths to the reference circuit. Getting signals in and out of an IC chip at high frequency is usually limited by the parasitic and the mismatch of the impedance of the lines that carry the signal and the I/O port of the IC. This impedance mismatch causes reflections of signals that translate to distorted signals and power loss. The mismatch impedance is addressed in the system level by assembling impedance matching elements (L,C) in close proximity to the I/Os of the IC chip thus matching the I/O impedance to the signal line impedance. However, this solution is not applicable in conventional probe testing due to the large distance between the probe contact point and the reference elements.
In summary, the relative remoteness between the IC device under test and the reference circuit components causes impairment of the test signals, particularly for high-speed RF signals.
Similar challenges are presented in testing high speed digital IC devices. Very dense memory IC chips are most reliably tested when the test address signals have short electrical paths.